Referenced Items are not available for this document.
This paper proposes a novel array architecture for full-search block matching motion estimation. The design efforts are focused on transforming the array computation in a way that minimizes the memory and I/O costs while satisfying the highest throughput requirements. Compared with the existing architectures, this one ensures feasible solutions for the HDTV picture format with twice lower memory requirements, minimal I/O pin count and 100% processor utilization. The architecture features regular and simple interconnects and is quite suitable for VLSI implementation
Published in:
Acoustics, Speech, and Signal Processing, 1997. ICASSP-97., 1997 IEEE International Conference on
(Volume:5
)
Date of Conference: 21-24 Apr 1997
- Page(s):
- 4109 - 4112 vol.5
- Meeting Date :
- 21 Apr 1997-24 Apr 1997
- ISSN :
- 1520-6149
- Print ISBN:
- 0-8186-7919-0
- INSPEC Accession Number:
- 5760087
- Conference Location :
- Munich
- Digital Object Identifier :
- 10.1109/ICASSP.1997.604850
- Product Type:
- Conference Publications
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