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A comma detection and word alignment circuit is proposed for a 6.25-Gb/s SerDes. In order to achieve a high speed, a new architecture of combined parallel and pipelined is employed. Based on the proposed structure, a high speed comma detector is implemented using 0.18 μm CMOS technology. Post simulation result indicates that the circuit can operates up to 770MHz with a power consumption of 10.8 mW under 1.8V power supply.