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A phase-locked loop (PLL) with the proposed voltage-controlled oscillator (VCO) and a divide-by-2 injection-locked frequency divider (ILFD) is fabricated in 65-nm digital CMOS technology. The proposed VCO and the divide-by-two ILFD operate at the higher and lower poles, respectively, of two fourth-order LC ladders. The frequency ratio between the VCO and its first divide-by-2 ILFD is kept by scaling the inductances and the capacitances. The design considerations of this VCO and the locking range of this ILFD are discussed. The measured locking range of this PLL is 132.1-132.6 GHz. It consumes 120.8 mW from 1.35-V supply, excluding the output buffers. The chip area is 0.96 × 0.92 mm2.