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The evolution toward software-defined radio (SDR) technologies, in particular, cognitive radios, is leading toward the need to support multiple radio solutions with the same baseband processing resources. This implies not only a huge design effort, but also a shift from hardware to software design flavored tool chains. In this paper, a hardware complexity and energy dissipation are analyzed by implementing three programmable processor architectures that support 32- and 12-bit floating-point and 16-bit fixed-point arithmetics. The processors are based on the transport triggered architecture (TTA) that has a very low programmability overhead. We programmed a recently introduced selective spanning with fast enumeration (SSFE) soft-output detector for these processors. The processors are capable to achieve data rates required in multiple-input multiple-output orthogonal frequency- division multiplexing (MIMO-OFDM) 3G LTE system with a small energy dissipation. The analysis shows that at the same goodput rate a floating-point implementation can achieve a lower gate count and a better power efficiency than a fixed-point design. Combined with tool chain benefits, the floating-point arithmetic is becoming attractive for future SDR solutions.
Selected Topics in Signal Processing, IEEE Journal of (Volume:5 , Issue: 8 )
Date of Publication: Dec. 2011