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Determinant factors of the minimum operating voltage (VDDmin) of CMOS logic gates are investigated by measurements of logic-gate chains in 65nm CMOS. VDDmin consists of a systematic component (VDDmin(SYS)) and a random variation component (VDDmin(RAND)). VDDmin(SYS) is minimized, when the logic threshold voltage of logic gates equals to half supply voltage (VDD). The tuning of the logic threshold voltage of each logic gate is achieved by the sizing of the gate width of nMOS/pMOS. VDDmin(RAND) is minimized by reducing the random threshold variation achieved by increasing the gate width or the forward body biasing. In addition, the temperature dependence of VDDmin is measured for the first time. The temperature for the worst corner analysis for VDDmin should be changed depending on the number of gate counts of logic circuits.