A 100–117 GHz W-Band CMOS Power Amplifier With On-Chip Adaptive Biasing

A W-band power amplifier (PA) has been realized in 65 nm bulk CMOS technology, which covers 100 to 117 GHz. It delivers up to 13.8 dBm saturated output power with up to 15 dB power gain and 10% PAE, which also achieves better than 10.1 dBm output P1 dB. The PA features compact realization with transformer-coupled three stages and on-chip input/output baluns to facilitate single-ended characterization. To ensure stability and boost efficiency, it adopts cascode structure in the first two stages and common source amplifier in the last stage. To improve the PAE and linearity, an adaptive biasing circuitry is incorporated inside the PA. The entire PA core occupies 0.041 mm
²
die area and burns about 180 mW with the adaptive bias circuit consuming only 0.002 mm
²
active chip area.