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This paper presents a low-power adaptive 60 GHz baseband in 65 nm CMOS. The design integrates variable gain amplifiers, analog phase rotator, 40-coefficient I/Q decision feedback equalizers (DFEs), clock generation and data recovery circuits, and adaptation hardware. The baseband achieves 10 Gb/s while consuming 53 mW (DFE adaptation on)/45 mW (DFE adaptation off), representing ~10 X improvement in data-rate and power efficiency over prior art.
VLSI Circuits (VLSIC), 2011 Symposium on
Date of Conference: 15-17 June 2011