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Due to upcoming power and robustness issues related to decananometer silicon technologies, neuromorphic architectures are increasingly meaningful to perform computation on some specific classes of applications such as signal processing. Such architectures require low-power, compact, and robust hardware spiking neurons. We propose an analog implementation in CMOS 65 nm process of a Leaky Integrate-and-Fire Neuron that fulfills all of these requirements. Results show that neuron area is (100 /μm2), and simulated precision under severe process variability is 35 dB. As a consequence, this neuron is well suited for computational purposes.
Date of Conference: 26-29 June 2011