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Embedded package wafer bow elimination techniques

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6 Author(s)
J. Thompson ; Draper Laboratory 555 Technology Square Cambridge, MA 02139 ; G. Tepolt ; L. Racz. A. Mueller ; T. Langdo
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We outline several approaches to allow individual die to be encapsulated within a silicon substrate, which we define as a cavity wafer, without causing wafer bow. This technique forms the basis for a novel integrated ultra high density (i-UHD) wafer-level packaging platform. The iUHD process begins with a standard Si wafer that is patterned and dry etched to form cavities that accept buried components. After etching, the wafer is blanket metalized. Individual commercial off-the-shelf (COTS) die are placed onto an adhesive film and precision transferred to the substrate wafer. Low coefficient of thermal expansion (CTE) encapsulant is injected into the cavity surrounding the die. Finally, the adhesive film is removed to reveal a planar surface on the reconstructed core wafer. Multilayer interconnect is fabricated on both sides of the core using standard wafer fabrication techniques. A challenge to this approach has been that curing and shrinkage of the encapsulant, as well as its CTE mismatch with silicon, creates wafer bow. In this paper we present a technique that eliminates bow by mirroring the die-side wafer cavities about the neutral bending axis.

Published in:

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

Date of Conference:

May 31 2011-June 3 2011