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Embedded memory fail analysis for production yield enhancement

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8 Author(s)
Baltagi, Y. ; STMicroelectronics ZI Rousset, Rousset, France ; Rosi, D.L. ; Tancorre, V. ; Garagnon, C.
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The traditional approach for memory fail bitmap analysis is to identify the topological signatures and perform a Failure Analysis investigation on the most frequent signatures, based on the (x, y) coordinates of the fails. This approach is inappropriate when a large portion of the fails are single bits, because too many investigations are required to statistically identify the major repetitive failure mechanisms. This becomes a problem for fast product development and production yield ramp. This paper presents a methodology to classify single fail bits by their unique fault signature, based on the sequence of failing march element read operations from multiple data backgrounds, in a standard Memory BIST flow. These classifications allow investigations to focus on the most important failure mechanisms with greatest yield impact. The methodology is demonstrated in an industrial environment, with identification of critical yield detractors. Starting from a yield problem associated to MBIST failures at high operating temperature, the fault signatures were used to identify a static noise margin parametric problem and a dislocation fault physical problem.

Published in:

Advanced Semiconductor Manufacturing Conference (ASMC), 2011 22nd Annual IEEE/SEMI

Date of Conference:

16-18 May 2011