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Scaling with Design Constraints: Predicting the Future of Big Chips

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4 Author(s)
Wei Huang ; IBM Res., Austin, TX, USA ; Rajamani, K. ; Stan, M.R. ; Skadron, K.

The past few years have witnessed high-end processors with increasing numbers of cores and larger dies. With limited instruction-level parallelism, chip power constraints, and technology-scaling limitations, designers have embraced multiple cores rather than single-core performance scaling to improve chip throughput. This article examines whether this approach is sustainable by scaling from a state-of-the-art big-chip design point using analytical models.

Published in:

Micro, IEEE  (Volume:31 ,  Issue: 4 )

Date of Publication:

July-Aug. 2011

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