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A systematic design approach using signal flow graph (SFG) is presented in this paper, tailored for integrated reconfigurable switched-capacitor (SC) power converters. To achieve an optimal power stage, an unified signal flow graph (USFG) model is developed. System transfer function and I/O impedance can be evaluated based on it. To verify the design approach, the paper demonstrates a step-up/down reconfigurable SC power converter with five optional gain ratios. A dual-loop control scheme is employed to reconfigure the converter according to the instantaneous line/load conditions. A low-power, digital controller is designed in the subthreshold region for the feedback control loop. The converter was fabricated with a 130-nm CMOS process. Experimental results show that its output can be continuously regulated from 0.4 to 2.2 V, while allowing the input voltage to randomly vary between 0.9 and 1.5 V. The line regulation is maintained below 1.4%, with a lowest value of 0.07%. The maximum efficiency of 90.22% is measured at 0.55-V output voltage and 20-mW load.