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Speculative completion for the design of high-performance asynchronous dynamic adders

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4 Author(s)
S. M. Nowick ; Dept. of Comput. Sci., Columbia Univ., New York, NY, USA ; K. Y. Yun ; P. A. Beerel ; A. E. Dooply

This paper presents an in-depth case study in high-performance asynchronous adder design. A recent method, called “speculative completion”, is used. This method uses single-rail bundled datapaths but also allows early completion. Five new dynamic designs are presented for Brent-Kung and Carry-Bypass adders. Furthermore, two new architectures are introduced, which target (i) small number addition, and (ii) hybrid operation. Initial SPICE simulation and statistical analysis show performance improvements up to 19% on random inputs and 14% on actual programs for 32-bit adders, and up to 29% on random inputs for 64-bit adders, over comparable synchronous designs

Published in:

Advanced Research in Asynchronous Circuits and Systems, 1997. Proceedings., Third International Symposium on

Date of Conference:

7-10 Apr 1997