Referenced Items are not available for this document.
A novel asynchronous design method is introduced which combines the area efficiency of bundled data with data dependent computation time. The design of a 16×16 bit multiplier using this technique is explained and evaluated. Simulation results show that area time savings of 20% compared to an equivalent synchronous design can be achieved
Published in:
Advanced Research in Asynchronous Circuits and Systems, 1997. Proceedings., Third International Symposium on
Date of Conference: 7-10 Apr 1997
- Page(s):
- 186 - 197
- Meeting Date :
- 07 Apr 1997-10 Apr 1997
- Print ISBN:
- 0-8186-7922-0
- INSPEC Accession Number:
- 5572991
- Conference Location :
- Eindhoven
- Digital Object Identifier :
- 10.1109/ASYNC.1997.587174
- Product Type:
- Conference Publications
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