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A quasi delay-insensitive bus proposal for asynchronous systems

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2 Author(s)
P. A. Molina ; Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK ; P. Y. K. Cheung

The composability dimension of asynchronous circuits is extended to incorporate delay-insensitivity, area utilisation and layout complexity. The disadvantages of conventional delay-insensitive data paths are established, and an alternative solution based on tri-state buffers is presented. The solution maintains the same delay-insensitivity while achieving a significant reduction in circuit area utilisation and layout complexity of the data path

Published in:

Advanced Research in Asynchronous Circuits and Systems, 1997. Proceedings., Third International Symposium on

Date of Conference:

7-10 Apr 1997