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A high-speed median circuit

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2 Author(s)
Opris, I.E. ; Center for Integrated Syst., Stanford Univ., CA, USA ; Kovacs, G.T.A.

A high-speed analog median circuit is presented using a two-stage architecture to minimize the errors around the transition corners. Prototypes have been designed and built using the Orbit 2-μm CMOS process. The design has been optimized for low crossover distortion and fast transient recovery in less than 200 ns. The active area is 0.2 mm 2, and the circuit dissipates 7 mW from a single 5 V supply while being able to drive an external 30 pF capacitor

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:32 ,  Issue: 6 )

Date of Publication:

Jun 1997

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