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Power consumption optimization of 8 bit, 2 MHz voltage scaling subranging CMOS 0.5 μm DAC

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3 Author(s)
F. Maloberti ; Dipt. di Elettronica, Pavia Univ., Italy ; R. Rivoir ; G. Torelli

We present the design of an 8-bit voltage-scaling, subranging digital-to-analog converter with a current-biased floating fine ladder. The basic structure has been analyzed and optimized for the best trade-off between conversion speed and power dissipation. This allowed us to design a 4+4 bit converter capable to drive 4 pF with 200 μA current consumption running at 2 MHz. Circuit simulations on a 0.5 μm, 3.3 V single-supply CMOS digital process show that the above performances are fully achieved even in worst-case process conditions

Published in:

Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on  (Volume:2 )

Date of Conference:

13-16 Oct 1996