By Topic

High throughput systolic memory architecture using three directional dataflows

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Gab Joong Jeong ; Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea ; Kyoung Hwan Kwon ; Moon Key Lee ; Seung Han An

This paper describes a new scalable systolic memory architecture. It provides low initial latency and high throughput using three directional systolic dataflows. The throughput is determined not by the entire memory size of designed chip but by the size of a single submemory block element. Pipelined address decoding reduced the access time of a single sub-memory block. It supports scalability by regular operations of all elements. We designed 4k-bit sized prototype which operates at 77 Mhz

Published in:

Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on  (Volume:2 )

Date of Conference:

13-16 Oct 1996