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A testable CMOS asynchronous counter

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2 Author(s)
Carson, G. ; Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA ; Borriello, G.

A testable design for an asynchronous n-bit CMOS counter is presented, with test inputs that provide full coverage for stuck-at and stuck-open faults. The test time is O(n) where the counter outputs are not observable, compared to O(n 2) for a synchronous counter. Three control signals are required for the testable counter as opposed to one reset signal for the base counter. The testable counter incorporates a scan path, utilizing the state storage in the counter cells, whereby the counter is converted into an n-bit master-slave asynchronous shift register with the counter's request input being used as the shift-register input. The only observable outputs are acknowledge and carry-out signals. The counter utilizes two-cycle (transition) signaling and guarantees that new output values are available before acknowledge is toggled. Two 16-b counters, one base design and one scan-based design, were fabricated on the same chip (2.0-μm n-well CMOS) through MOSIS. Four parts were received, all of which passed the test suites developed

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 4 )