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A fault-tolerant associative memory with high-speed operation

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3 Author(s)
H. Bergh ; Ericsson Telecom AB, Stockholm, Sweden ; J. Eneland ; L. -E. Lundstrom

An 8-kb (128-word×64-b) CMOS associative memory with word and bit-parallel operation is described. The highly parallel and pipelined architecture is optimized for high-speed associative operations. The data processing capability is one word/cycle corresponding to 16 MIPS at a typical cycle time of 60 ns. The memory is fault tolerant under software control. A faulty word location in the memory can be made inaccessible by on-chip circuitry. The device is a complete single-chip associative memory with internally controlled addressing and associative data as output

Published in:

IEEE Journal of Solid-State Circuits  (Volume:25 ,  Issue: 4 )