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Thermomechanical stresses in an underfilled flip chip DCA

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3 Author(s)
Le Gall, C.A. ; Sandia Nat. Labs., USA ; Qu, J. ; McDowell, D.L.

Flip chip interconnection technology has recently been extended to direct chip attach (DCA) to organic printed wiring boards (PWBs). However, the coefficient of thermal expansion (CTE) of the PWB is almost an order of magnitude greater than that of the silicon die; under operating conditions, this mismatch subjects the solder joints to cyclic stresses, which may result in mechanical fatigue failure of the solder connections. Such CTE mismatch-induced stresses, manifested by the increasing die size and temperature excursions, have posted a great challenge to the thermomechanical reliability of flip-chip DCA packages. To prevent premature thermomechanical failure and ensure the reliability of a DCA package, the thermomechanical stresses caused by the CTE mismatch, which is the driving force to failure, must be understood. Furthermore, design and processing technologies must be developed to minimize such stresses. In this paper, a general methodology is developed to conduct stress analysis in flip-chip DCA with underfill encapsulation using the finite element method. In particular, two fundamental issues are addressed, namely, effects of die size on the stress fields and the optimization of thermomechanical properties of underfill materials. It is shown in this paper that the nature of stress fields in underfilled flip chips is fundamentally different from that in any other surface mount assemblies. The distance to neutral point (DNP) is no longer a dominant factor in determining the magnitude of the stresses in underfilled flip-chip packages. Consequently, as far as the stresses are concerned, the die size is not a limiting factor. The underfill optimization studies have demonstrated that both stress and strain fields should be considered in the analysis of a flip chip assembly. Some general guidelines have been provided for selecting optimal CTE and modulus values which minimize stress and strain fields in the solder and silicon chip

Published in:

Advanced Packaging Materials. Proceedings., 3rd International Symposium on

Date of Conference:

9-12 Mar 1997