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GM Plan: a gate matrix layout algorithm based on artificial intelligence planning techniques

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2 Author(s)
Yu Hen Hu ; Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA ; Sao-Jie Chen

The CMOS gate matrix layout problem is formulated and solved as an artificial intelligence planning problem in which a plan (the solution algorithm) is to be generated to achieve a goal (the gate matrix layout). The overall goal consists of many subgoals, each of which corresponds to the placement of a gate to a slot, and to the routing of associated nets connecting to that gate. As different nets compete for track (resource) usage, these subgoals interact (interfere) with each other, rendering suboptimal solutions. Here, such interaction among subgoals is managed with two artificial intelligence planning techniques: hierarchical subgoal organization and domain-independent search control policies. The subgoal hierarchy facilitates an object classification of the subgoals into priority classes according to a proposed distance measure of connectivity. Two search control policies (general problem-solving heuristics)-most-constraint (MC) and least impact (LI)-are used to guide the search process. A planning-based gate matrix layout algorithm, called GM Plan, which combines the gate placement and net routing into a single, incremental, problem-solving loop has been developed using these techniques. Encouraging results have been observed in a number of test examples

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:9 ,  Issue: 8 )