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Stress/stain assessment and reliability prediction of through silicon via and trace line structures of 3D packaging

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4 Author(s)
Ting-Hsin Kuo ; Dept. of Power Mech. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Yen-Fu Su ; Chung-Jung Wu ; Kuo-Ning Chiang

This study assesses the reliability life of 3D chip stacking packaging developed by the Industrial Technology Research Institute (ITRI). The simulation results show that the trends of stress of through silicon via (TSV) structures with different chip stacking numbers are nearly constant during thermal stress analysis. Therefore, the simplified two-layer chip stacking model is adopted to analyze the thermal-mechanical behavior of TSV. Subsequent thermal cycle simulations show that the maximum equivalent plastic strain occurs at the bottom trace near the substrate. The Engelmaier model is selected to predict the fatigue life of TSV, and it shows that the simulation results match experimental results. The effects of the substrate material and underfill are also discussed. TSV structures with BT substrates, which can replace silicon substrates, could effectively protect bottom traces and prevent fractures occurring from copper trace. In addition, when a TSV structure with an underfill is subjected to thermal cycle conditions, chips and vias experience more stress, but copper traces are protected by the underfill. No apparent alteration in reliability performance is detected.

Published in:

Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2011 12th International Conference on

Date of Conference:

18-20 April 2011