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Design of a Dual W- and D-Band PLL

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7 Author(s)
Shahriar Shahramian ; Bell Laboratories, Alcatel-Lucent, Murray Hill, NJ, USA ; Adam Hart ; Alexander Tomkins ; Anthony Chan Carusone
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This paper describes the design considerations and performance of the highest frequency phase-locked loop (PLL) reported to date. The PLL was fabricated in a 0.13-μm SiGe BiCMOS process and integrates on a single die: a fundamental-frequency 86-92 GHz Colpitts voltage-controlled oscillator (VCO), a differential push-push 160-GHz Colpitts VCO with two differential outputs at 80 GHz, a programmable divider chain, the charge pump, and all loop filter components. It achieves the lowest W- and D-band phase noise of -93 dBc/Hz at 90 GHz and -87.5 dBc/Hz at 163 GHz, both measured at a 100 kHz offset, and demonstrates an extended locking range of 80-100 GHz at the fundamental frequency, and 160-169 GHz at the second harmonic output of the push-push VCO. The single-ended PLL output power is -3 dBm at 90 GHz and -25 dBm at 164 GHz. The chip consumes 1.25 W from 1.8 V, 2.5 V, and 3.3 V supplies and occupies 1.1 mm × 1.7 mm, including pads.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:46 ,  Issue: 5 )