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A 130- \mu W, 64-Channel Neural Spike-Sorting DSP Chip

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3 Author(s)
Vaibhav Karkare ; Department of Electrical Engineering, University of California, Los Angeles, CA, USA ; Sarah Gibson ; Dejan Markovic

Spike sorting is an important processing step in various neuroscientific and clinical studies. Energy-efficient spike-sorting ASICs are necessary to allow real-time processing of multi-channel, wireless neural recordings. Spike-sorting ASICs have to meet stringent power-density constraints and must provide significant data-rate reduction for wireless transmission. Most existing designs either provide only spike detection for multi-channel processing, or they provide detection and feature extraction only for a single channel. In this paper, we demonstrate the design of a spike-sorting DSP chip that can perform detection, alignment, and feature extraction simultaneously for 64 channels. Spike-sorting algorithms chosen based on a complexity-performance analysis were implemented on ASIC using a MATLAB/Simulink-based architecture design framework. Energy-delay tradeoffs of the design were analyzed to identify the optimal degree of interleaving. The chip was implemented with a modular architecture, and can be configured to process 16, 32, 48, or 64 channels. Inactive cores are power-gated when the chip is operated to process a reduced number of channels. The chip, implemented in a 90-nm CMOS process, has a power dissipation of 130 μW (power density of 30 μW/mm2) when processing all 64 channels and provides a data-rate reduction of 91.25% (11.71 Mb/s to 1.02 Mb/s).

Published in:

IEEE Journal of Solid-State Circuits  (Volume:46 ,  Issue: 5 )