Referenced Items are not available for this document.
A 10-bit 70-MS/s D/A (digital-to-analog) converter fabricated in a 1-μm CMOS process is described. A linearity within ±0.5 LSB has been realized by a new switching sequence that is based on hierarchical error cancellation and suppresses both graded and symmetrical errors distributed in outputs of current sources. A layout technique for suppressing the influence of transistors implanted in tilt angles on linearity is also discussed
Published in:
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Date of Conference: 7-9 June 1990
- Page(s):
- 57 - 58
- INSPEC Accession Number:
- 3887453
- Conference Location :
- Honolulu, Hawaii, USA
- Digital Object Identifier :
- 10.1109/VLSIC.1990.111093
- Product Type:
- Conference Publications
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