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A 3.5 ns, 2 K×9 self timed SRAM

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3 Author(s)

A self-timed SRAM of 18-Kb density has been developed. It has several value-added features for specialty computer CPU applications. This part has an access time of 3.5 ns and a cycle time of less than access. All inputs are registered with respect to the clock positive edge, and read and write operations are internally self-timed. The output latch self-loads internally, thus insuring that data are valid for the entire cycle. The external timing facilities system usage. The part is formed using a self-timed synchronous architecture. An innovative circuit method called postcharge logic that allows a CMOS technology to achieve gate delays roughly equivalent to ECL (emitter coupled logic) gate delays was employed. Gate delays of 105 ps have been observed, compared to 145 ps for a regular CMOS inverter

Published in:

VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on

Date of Conference:

7-9 June 1990