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A 13 bit 2.5 MHz self-calibrated pipelined A/D converter in 3 μm CMOS

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3 Author(s)

A self-calibrated pipelined A/D (analog-to-digital) converter technique potentially applicable in high-resolution video applications is described. This approach potentially requires much less area than multistep flash approaches and requires fewer clock cycles than error averaging techniques. Since self-calibration can be performed during interframe intervals, this approach is particularly attractive for video applications. A 3-μm CMOS prototype fabricated for feasibility evaluation using this architecture achieves 13-b resolution at 2.5 Msample/s, consumes 100 mW, and occupies 40 K mil2, with a single 5-V supply and a two-phase nonoverlapping clock. A sampling rate of 15 MHz and an area of about 10 K mil2 can be projected from these results in a 1-μm implementation

Published in:

VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on

Date of Conference:

7-9 June 1990