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This paper presents the simulation and experimental measurements of an electrical test structure that can be used to assess the degree of planarization of interlayer dielectrics. It consists of two sets of metal combs separated by a dielectric. For each structure the combs on the two layers overlap each other, with adjacent structures having the overlap in one direction progressionally offset by 0.2 μm. The capacitance of these structures is then measured, from which the degree of planarization can be assessed. This structure has potential applications for characterising chemical mechanical polishing (CMP) processes for multilevel very large scale integration (VLSI) applications
Published in:
Semiconductor Manufacturing, IEEE Transactions on
(Volume:10
,
Issue:
2
)
Date of Publication: May 1997
- Page(s):
- 242 - 249
- ISSN :
- 0894-6507
- INSPEC Accession Number:
- 5570263
- Digital Object Identifier :
- 10.1109/66.572076
- Date of Current Version :
- 06 August 2002
- Issue Date :
- May 1997
- Sponsored by :
- IEEE Components, Packaging and Manufacturing Technology Society
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