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High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

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22 Author(s)
J. C. Lin ; Research and Development, Taiwan Semiconductor Manufacturing Company, Ltd. 8, Li-Hsin Rd. 6, Hsinchu Science Park, Taiwan 30077, R.O.C. ; W. C. Chiou ; K. F Yang ; H. B. Chang
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Technology challenges and solutions in the development and fabrication of high-density three dimensional (3D) chip integration structures have been investigated. Critical 3D integrated circuit (IC) enabling technologies, such as through silicon via (TSV), wiring and redistribution layer (RDL), wafer thinning and handling, micro-bump (μ-bump) processes and joining, that form the building blocks for 3D IC technology were developed based on established Si foundry technologies. Test vehicles (TV's) have been designed to develop and optimize the processes, structures, as well as to evaluate the performance, yield and reliability of the 3D integration scheme.

Published in:

Electron Devices Meeting (IEDM), 2010 IEEE International

Date of Conference:

6-8 Dec. 2010