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This paper presents a 100 kS/s, 1.3 μW, 9.3 ENOB successive approximation ADC with a time-domain comparator. The proposed time-domain comparator utilizes a differential multi-stage VCDL, resulting in a highly digital operation eliminating static power consumption. The effects of gain, noise, and offset are also investigated by detailed analysis which proves the feature of reducing the input-referred noise and offset by simply increasing the number of delay stages. For verification, the proposed ADC is fabricated in a 0.18 μm CMOS. With a single supply voltage of 0.6 V, the ADC consumes 1.3 μW at the maximum sampling rate of 100 kS/s. The measured ENOB is 9.3 b showing a figure of merit of 21 f J/conversion-step.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:46
,
Issue:
3
)
Date of Publication: March 2011
- Page(s):
- 651 - 659
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 11833891
- Digital Object Identifier :
- 10.1109/JSSC.2010.2102590
- Product Type:
- Journals & Magazines
- Date of Publication :
- 28 January 2011
- Date of Current Version :
- 22 February 2011
- Issue Date :
- March 2011
- Sponsored by :
- IEEE Solid-State Circuits Society
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