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Testable Path Selection and Grouping for Faster Than At-Speed Testing

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3 Author(s)
Xiang Fu ; Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China ; Huawei Li ; Xiaowei Li

Faster than at-speed testing provides an efficient way for testing of small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of patterns is managed to be applied at certain frequency. In this paper, we propose to generate tests for faster than at-speed testing based on path delay fault (PDF) model and single path sensitization criterion. An effective testable path selection and grouping method is introduced, which could quickly and accurately identify paths whose delay falls into a given delay span. Several techniques are used to improve the efficiency of the testable path selection procedure. Experimental results on ISCAS'89 benchmark circuits show that the proposed method could achieve high transition fault coverage and high test quality of SDDs with low CPU time.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:20 ,  Issue: 2 )