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Impact of partial reset on fault independent testing and BIST

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3 Author(s)
Huy Nguyen ; Georgia Inst. of Technol., Atlanta, GA, USA ; R. Roy ; A. Chatterjee

Partial reset has been shown to have significant impact on deterministic test generation for sequential circuits. In this paper we explore the use of partial reset in fault-independent testing and application to built-in self-test. We take the following approach: based on fault propagation analysis, we select a subset of the circuit flip-flops to be initialized to 0 or 1. The initialization (set/reset) is performed periodically while the test input vectors to the sequential circuit are applied. An average improvement of 15% in fault-coverage has been obtained for circuits resistant to random pattern testing

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997