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Faster fault simulation through distributed computing

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3 Author(s)
Ravikumar, C.P. ; Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India ; Jain, V. ; Dod, A.

In this paper, we describe distributed algorithms for combinational fault simulation assuming the classical stuck-at fault model. Our algorithms have been implemented on a network of Sun workstations under the Parallel Virtual Machine (PVM) environment. Two techniques are used for subdividing work among processors -test set partition and fault set partition. The sequential algorithm for fault simulation, used on individual nodes of the network, is based on a novel path compression technique proposed in this paper. We describe experimental results on a number of ISCAS '85 benchmark circuits

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997