By Topic

An Offset Double Conversion Technique for Digital Calibration of Pipelined ADCs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Bei Peng ; Beijing University of Technology, Beijing 100022, China ; Hao Li ; Pingfen Lin ; Yun Chiu

An offset double conversion technique to calibrate pipelined analog-to-digital converters (ADCs) is presented, in which self-equalization is performed using one ADC, resulting in fast convergence for high-resolution applications. The approach also promises significant improvement of signal-to-noise-plus-distortion ratio (SNDR), simultaneous multistage calibration, and minimal analog circuit modification. The design tradeoffs involved in this technique, especially the conversion rate reduction, are discussed in detail. Behavioral simulation results are presented to demonstrate the effectiveness of the technique, in which the learning of 39 error parameters is simultaneously accomplished with SNDR and spurious-free dynamic range improvements from 43 and 52 dB to 90 and 108 dB, respectively, for a 15-bit pipelined ADC.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:57 ,  Issue: 12 )