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Fan-Out Wafer-Level Packaging with highly flexible design capabilities

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7 Author(s)

We have developed a new Fan-Out Wafer-Level Packaging (FO-WLP) technology with flexible design capabilities for multilayer fan-out redistribution layers (RDLs) connected to the fine-pitch I/O pads of chips. The prototype of a 2.0 mm × 2.0 mm FO-WLP with 25-pin land grid array (LGA) including a 1.6 mm × 1.6 mm microcontroller chip was fabricated and evaluated. Board-level reliability was also confirmed using 5.0 mm × 5.0 mm FO-WLP. This technology is suited for applications in extremely small microcomputer chip/system packaging for ubiquitous computing.

Published in:

Electronic System-Integration Technology Conference (ESTC), 2010 3rd

Date of Conference:

13-16 Sept. 2010