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Thin wafer processing and chip stacking for 3D integration

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4 Author(s)
T. Matthias ; EV Group, DI Erich Thallner Strasse 1, 4782 St. Florian/Inn, Austria ; B. Kim ; M. Wimplinger ; P. Lindner

The advantages as well as the technical feasibility of through silicon vias (TSV) and 3D integration have been widely acknowledged by the industry. Today the major focus is on the manufacturability and on the integration of all the different building blocks for TSVs and 3D Interconnects. In this paper the advances in the field of thin wafer processing and wafer bonding are presented with emphasis on the integration of all these process steps.

Published in:

Electronic System-Integration Technology Conference (ESTC), 2010 3rd

Date of Conference:

13-16 Sept. 2010