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Nonvolatile Memory Partitioning Scheme for Technology-Based Performance-Reliability Tradeoff

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4 Author(s)
Zambelli, C. ; Dipt. di Ing., Univ. degli Studi di Ferrara, Ferrara, Italy ; Bertozzi, D. ; Chimenton, A. ; Olivo, P.

The need to improve nonvolatile memories reliability in embedded systems is a key design concern. We here propose a methodology, managed by the memory controller, that optimizes the data reliability at the physical level for critical data whereas exploiting the transaction performances for noncritical data. The reliability-performance tradeoff is obtained by partitioning the memory addressable space in different functional blocks, each on written by means of a specific optimized writing algorithm. The method feasibility is demonstrated by a case study exploiting phase change memories (PCMs) features.

Published in:

Embedded Systems Letters, IEEE  (Volume:3 ,  Issue: 1 )

Date of Publication:

March 2011

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