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The paper integrates the results of the previous work and presents the complete methodology for synthesis of digital circuits and systems from hierarchical and parallel specifications expressed in the form of hierarchical graph-schemes. Such specifications provide support for design reuse, parallelization and other important features highlighted in the paper. The synthesis is based on the model of a hierarchical finite state machine (HFSM) and the proposed design templates. Two different types of HFSM (with explicit and implicit modules) are discussed. Practicability and advantages of the proposed technique are demonstrated on numerous examples, such as data sorting, priority buffering and embedded controllers.
Electronics Conference (BEC), 2010 12th Biennial Baltic
Date of Conference: 4-6 Oct. 2010