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Threshold voltage shift and drain current degradation by NBT stress in Si (110) pMOSFETs

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6 Author(s)
Ota, K. ; Adv. LSI Technol. Lab., Toshiba Corp., Yokohama, Japan ; Saitoh, M. ; Nakabayashi, Y. ; Ishihara, T.
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Threshold voltage shift and drain current degradation by NBT stress in Si (100) and (110) pMOSFETs are systematically studied. Threshold voltage shift in (110) pFET is larger than that in (100) pFET. However, time and temperature dependence of NBTI suggest that the mechanisms of the NBTI degradation are independent of the surface orientations. It is newly found that the drain current degradation in (110) pFET is severer than that in (100) pFET even when the same amount of charges at the interface is generated. This can be explained by larger mobility degradation in (110) pFETs due to the generated interface traps.

Published in:

Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European

Date of Conference:

14-16 Sept. 2010