Referenced Items are not available for this document.
A simple approach for manufacturing quasi-planar tri-gate bulk MOSFET structures is demonstrated and shown to be effective for reducing variation in 6T-SRAM read and write margins, in an early 28nm CMOS technology. With optimization of the pocket implant doses, quasi-planar bulk CMOS technology can facilitate voltage scaling. It also provides a means to achieve high yield with a notch-less 6T-SRAM cell layout, to facilitate area scaling.
Published in:
Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European
Date of Conference: 14-16 Sept. 2010
- Page(s):
- 142 - 145
- ISSN :
- 1930-8876
- Print ISBN:
- 978-1-4244-6658-0
- INSPEC Accession Number:
- 11626325
- Conference Location :
- Sevilla
- Digital Object Identifier :
- 10.1109/ESSDERC.2010.5618437
- Product Type:
- Conference Publications
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