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Tri-gate bulk CMOS technology for improved SRAM scalability

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13 Author(s)
Changhwan Shin ; Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA ; Nikolic, B. ; Tsu-Jae King Liu ; Chen Hua Tsai
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A simple approach for manufacturing quasi-planar tri-gate bulk MOSFET structures is demonstrated and shown to be effective for reducing variation in 6T-SRAM read and write margins, in an early 28nm CMOS technology. With optimization of the pocket implant doses, quasi-planar bulk CMOS technology can facilitate voltage scaling. It also provides a means to achieve high yield with a notch-less 6T-SRAM cell layout, to facilitate area scaling.

Published in:

Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European

Date of Conference:

14-16 Sept. 2010