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High Power-Supply-Rejection (PSR) Current-Mode Low-Dropout (LDO) Regulator

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2 Author(s)
Amit P. Patel ; Linear Technology Corporation, Milpitas, CA, USA ; Gabriel A. Rincon-Mora

Modern system-on-a-chip (SoC) solutions suffer from limited on-chip capacitance, which means that the switching events of functionally dense ICs induce considerable noise in the supplies. This ripple worsens the accuracy of sensitive analog electronics, such as ADCs, PLLs, and VCOs, etc. Without dropping a substantial voltage, point-of-load (PoL) low-dropout (LDO) regulators reduce (filter) this noise but only as much as their loop gains and bandwidths allow. This brief presents a 5-mA 1.5-μm bipolar current-mode LDO regulator that, with a higher bandwidth current loop, suppresses higher frequency noise by 49 dB (i.e., power-supply rejection) up to 10 MHz with only 68 nF at the output, which is 20 dB better than its voltage-mode counterpart.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:57 ,  Issue: 11 )