By Topic

Package thermal resistance: geometrical effects in conventional and hybrid packages

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Pence, W. ; Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA ; Krusius, J.P.

The effect of package geometry on thermal resistance for a set of six package configurations is studied. With thermal resistance network models it is possible to determine the junction-to-ambient thermal resistance for each package type under a variety of external cooling conditions. It is found that as the external package cooling technology improves, the thermal resistances for different package configurations separate into distinct ranges. In general, packages which have the lowest thermal resistance under free convection will have the largest thermal resistance under conditions of advanced forced liquid cooling, and vice versa. It is found that the surface area and internal thermal resistance serve as good indicators of thermal performance throughout the range from natural convection to microchannel cooling. On the basis of simple models, nonuniform chip active layer temperature distribution, spatially localized hot spot formation, and the effect of lower chip-to-ambient thermal resistance on the chip temperature profile are discussed

Published in:

Components, Hybrids, and Manufacturing Technology, IEEE Transactions on  (Volume:13 ,  Issue: 2 )