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Though silicon via (TSV) with parylene layer has many advantages, such as low temperature, CMOS matched low-temperature process and so on. In this paper, we use parylene layer as the sidewall to relieve the thermal stress in TSVs. Thermo-mechanical simulation of TSVs is performed to disscuss the effect of the parylene layer. It is found that the introduction of parylene layer can reduce the thermal stress in TSV, and this improvement tends to be larger when it is closer to the practical situation. We also discuss the effects of the temperature, the parylene thickness and the diameter of via on thermal stress distribution in TSVs. And it is indicated that as the parylene thickness increased, the thermal stress in TSVs decreased.