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Dynamic Power-Aware Mapping of Applications onto Heterogeneous MPSoC Platforms

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3 Author(s)
Andreas Schranzhofer ; Swiss Federal Institute of Technology (ETH), Zurich, Switzerland ; Jian-Jian Chen ; Lothar Thiele

Multiprocessor SOC platforms have been adopted for a wide range of high-performance applications, like automotive and avionic systems. Task assignment and processing unit allocation are key steps in the design of predictable and efficient embedded systems. Given the execution modes of applications, we propose a methodology to compute a task to processing element mapping, such that the expected average power consumption is minimized. Changing usage scenarios are represented by varying execution probabilities of modes. Statically precomputed template mappings for each execution probability are stored on the system and applied at runtime, allowing the system to adapt to changing environmental conditions. The underlying model considers static (leakage) and dynamic power. This study shows that deriving approximative solutions with a constant worst-case approximation factor in polynomial time is not achievable unless P = NP, even if a feasible task mapping is provided as an input. A polynomial-time heuristic algorithm is proposed that applies a multiple-step heuristic to derive template mappings. At runtime a manager monitors the system and chooses an appropriate precomputed template, hence low power-consumption is maintained over the systems lifetime. Experimental results reveal the effectiveness of the proposed algorithm by comparing the derived solutions to the optimal ones, obtained via an integer linear program (ILP).

Published in:

IEEE Transactions on Industrial Informatics  (Volume:6 ,  Issue: 4 )