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System level self-healing for parametric yield and reliability improvement under power bound

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7 Author(s)
Narasimhan, S. ; Dept. of EECS, Case Western Reserve U., Cleveland, OH, USA ; Paul, S. ; Chakraborty, R.S. ; Wolff, F.
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Post-silicon process compensation or “healing” of integrated circuits (ICs) has emerged as an effective approach to improve yield and reliability under parameter variations. In a System-on-Chip (SoC) comprising of multiple cores, different cores can experience different process shift due to local within-die variations. Furthermore, the cores are likely to have different sensitivities with respect to system power dissipation and system output parameters such as quality of service or throughput. Post-silicon healing has been addressed earlier at core level using various compensation approaches. In this paper, we present a system level healing algorithm for compensating SoC chips for a specific output parameter under power constraint. We formulate the healing problem as an ordinal optimization problem, where individual cores need to be assigned the right amount of healing that satisfies the target system performance and power requirement. Next, we propose an efficient solution to the problem using a priori design-time information about the relative sensitivities of the cores to system performance and power. Simulation results for example systems show that the proposed healing approach can achieve higher parametric yield and better settling time compared to conventional healing approaches.

Published in:

Adaptive Hardware and Systems (AHS), 2010 NASA/ESA Conference on

Date of Conference:

15-18 June 2010

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