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Minimizing energy consumption of a chip multiprocessor through simultaneous core consolidation and DVFS

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3 Author(s)
Ghasemazar, M. ; Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA ; Pakbaznia, E. ; Pedram, M.

This paper addresses the problem of minimizing the total energy consumption of a (chip) multiprocessor system while maintaining a required throughput. The minimum energy solution subject to a throughput constraint is achieved by selectively turning cores ON or OFF, assigning a given set of tasks to different cores, and simultaneously selecting the optimum operating supply voltage and clock frequency level for each processor core in the system. This NP-hard problem is solved by a three-level hierarchical framework comprised of a control theory-based dynamic power manager (DPM) and a task assignment unit. Experimental results demonstrate 17% energy saving of the proposed solution approach.

Published in:

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Date of Conference:

May 30 2010-June 2 2010

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