Referenced Items are not available for this document.
For a prescribed system performance, device, circuit and system design of a static CMOS datapath are conjointly optimized for different operating temperature ranges. Total power dissipation is reduced to one-third the value projected for 0.25 micron CMOS by the National Technology Roadmap for Semiconductors for a single datapath and to less than one-fourteenth the value projected for parallel datapaths assuming operation over a temperature range of 60°K above room temperature
Published in:
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Date of Conference: 23-27 Sep 1996
- Page(s):
- 313 - 316
- Meeting Date :
- 23 Sep 1996-27 Sep 1996
- ISSN :
- 1063-0988
- Print ISBN:
- 0-7803-3302-0
- INSPEC Accession Number:
- 5472767
- Conference Location :
- Rochester, NY
- Digital Object Identifier :
- 10.1109/ASIC.1996.552022
- Product Type:
- Conference Publications
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