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Low-power digital PLL with one cycle frequency lock-in time for clock syntheses up to 100 MHz using 32,768 Hz reference clock

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1 Author(s)
R. Fried ; Dept. of Electr. Eng., Swiss Federal Inst. of Technol., Zurich, Switzerland

A low-power Digital Phase Locked Loop (DPLL) with +/- 100 ps jitter, and one cycle frequency lock-in time is presented. It is used to generate clock frequencies up to 100 MHz using a reference frequency of 32,768 Hz, for advanced power management both at a device level and at a system level

Published in:

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Date of Conference:

23-27 Sep 1996