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A 400 megasample per second digital receiver ASIC

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5 Author(s)
Inkol, R. ; Defence Res. Establ., Ottawa, Ont., Canada ; Szwarc, V. ; Desormeaux, L. ; Esonu, M.
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An application specific integrated circuit has been designed to perform digital quadrature demodulation and other signal processing functions on digitized IF data in electronic warfare receivers. A fully pipelined, parallel architecture implemented on a GaAs gate array permits a nominal sampling rate of 400 megasamples per second. At this sampling rate the -3 dB bandwidth exceeds 80 MHz

Published in:

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Date of Conference:

23-27 Sep 1996